Mentor Graphics hiring freshers as Associate Applications Engineer – DFT at Bangalore

Mentor Graphics is a global technology leader in Electronic Design Automation, providing software and hardware design solutions that help engineers around the world innovate. Each year, our customers use tools of Mentor Graphics to push the boundaries of technology to deliver smaller, faster and more reliable products. They trust us with their technologies, we trust you to make them better. 

Job Description :

Company : Mentor Graphics

Job Title : Associate Applications Engineer – DFT – 2066

Job Location : India - Bangalore

Job Category : College

Job Details :

• In this position, you will be involved in a structured Associate Rotation Engineer Training Program. This is a fast-track training program that challenges you to develop the expertise needed to solve difficult technical problems.
• Associate Rotational Engineers are members of a team of highly motivated individuals working with customers designing the most complex hardware and software systems in the world and whose applications span the electronics industry. This training program will give you unique insight into our product marketing divisions and sales organization. Upon successful completion of the training program, you will be eligible to advance into one of these organizations.

Job Qualifications :

Requirements : 

Education : 

• BSEE/MSEE (Masters degree is preferred) Familiar with VLSI design, HDL Synthesis, VLSI testing and design for testability. 

Experience :

• Experience with design, simulation, verification of ASIC/VLSI circuits and systems, design verification and product test generation preferred.
• In-depth understanding of Design for Test (DFT) structures is required. 
• This includes scan based testing, Memory BIST, Logic BIST, and Boundary Scan (1149.1). Knowledge of scan data compression methodologies desired. 

Preferred experience in specific areas : 

• Operating Systems : UNIX, Linux, Sun Solaris. 
• Languages : Verilog (Behavioral, RTL, gate level), VHDL (Behavioral, RTL, gate level), Perl, C/C++. 
• CAD Tools : Synthesis, Simulation, ATPG, Memory BIST, Logic BIST, Boundary Scan. Familiarity with FastScan, FlexTest, LBISTArchitect, MBISTArchitect, and BSDArchitect a plus. 
• Strong trouble shooting skills and ability to break a complex problem into its components. 
• Excellent verbal and written communication skills
• very self-motivated and results-oriented
• Travel maybe required

CLICK HERE TO APPLY

Synopsys hiring B. Tech ECE / EEE freshers at Hyderabad and Bangalore

Business Title : CAE

Requisition Number : 5787BR

Hiring Locations :

INDIA - Bangalore

INDIA - Hyderabad

Job Category : Engineering

Hire Type : Employee

Job Description and Requirements :

Provides post-sales technical expertise during the installation, implementation, and maintenance of company products. May be involved in implementing detailed customer installation requirements. Ensures that client’s needs have been met and that the product/solution is fully functioning according to specification. May provide pre-sales support to company sales staff and customer personnel. The primiary responsibility will be to develop DRC/LVS/Fill/ERC runsets for IC Validator.

Has a basic overall understanding of the design process. Strong communication skills are required. Is proficient with UNIX, basic circuit layouts nd has a strong understanding of ASIC design flow, VLSI, and/or CAD engineering. Knowledge of competitive EDA tool products and product knowledge in any of the areas of Synthesis, Simulation, Verification, Place and Route, Design Reuse and/or Physical Design is preferred.

Typically requires no previous professional experience. Knowledge base generally acquired from a college degree or equivalent course training. Learns to use professional concepts. Applies company policies and procedures to resolve routine issues. Follows standard practices and specific, outlined, and detailed procedures in analyzing situations or data from which answers can be readily obtained. Normally receives detailed instructions on work, which is reviewed regularly by manager or more senior peers. Builds routine working relationships internally. Contacts are primarily with direct manager and other peers in the group or department.

About the company :

http://www.synopsys.com

Synopsys Inc. (Nasdaq:SNPS) provides products and services that accelerate innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor intellectual property (IP), Synopsys' comprehensive, integrated portfolio of system-level, IP, implementation, verification, manufacturing, optical and field-programmable gate array (FPGA) solutions help address the key challenges designers face such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in quickly bringing the best products to market while reducing costs and schedule risk. For more than 25 years, Synopsys has been at the heart of accelerating electronics innovation with engineers around the world having used Synopsys technology to successfully design and create billions of chips and systems. The company is headquartered in Mountain View, California, and has approximately 90 offices located throughout North America, Europe, Japan, Asia and India.

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Intel Internship for Mtech students at Bangalore

Job Title : Intern - VP IP Design and Verification

Location : Bangalore

Experience : 0-1 Yrs

Qualification : 

• Mtech student with good academic background from reputed institution (IIT/REC/RVCE/reputed university/college). 
• Should be available on site for one year project duration minimum 3 days a week for first six months. 
• Followed by this next six months possibly 5 days a week. E & C / CS is preferable. 
• Should have good analytical and programming skill set. 
• Programming in C and C++ is must. Hands on SystemC programming language is a plus.

Job Description :

Virtual Platform IP design and verification, release. Shall understand specification of the Intel Mobile chipset identified IP, develop the IP using programming language SystemC , develop test bench environment , test cases. Shall independently verify the developed IP, provide technical presentation to the lead on IP design, verification coverage, test results. Should have good analytical and programming skill set.Strong digital design skillset must. Programming in C and C++ is must. Hands on SystemC programming language is a plus.

About the company :

http://www.intel.in

Intel Technology India Pvt.Ltd focuses on creating innovative products that advance the next generation of technology. Intel with its strong technology heritage, provides an opportunity to work on cutting-edge technology, pushing the boundaries of innovation and transforming the way people live and work.

ST Microelectronics hiring B.Tech(Computer Science) as Associate Software Engineer

Job Title : Associate Software Engineer

Qualification : B.Tech(Computer Science)

Experience : 1 to 5 Yrs

Location : Greater Noida
Country : India
Job Ref. : 150416Function : Information Technologies

Job Description :

• Position is open for developer who will be working on web & mobile application development.
• Good academic background and problem solving skills.
• Responsible for design/coding and testing of applications.
• Application enhancement , maintenance and support to customer queries.
• Person will have a good exposure to business knowledge of online marketing of ST.

Skills required :

• Web technologies (java/jsp)
• html5
• css3
• mobile development
• Java
• Javascript
• Know how of spring framework & Oracle will be an added advantage

About the company :

http://www.st.com

• A world leader in providing the semiconductor solutions that make a positive contribution to people’s lives, both today and in the future
• Among the world’s largest semiconductor companies
• A leading Integrated Device Manufacturer serving all electronics segments
• A leading technology innovator (around 11,500 people working in R&D, ~16,000 patents, ~9,000 patent families and 515 new filings)
• Key strengths in Sense and Power, Automotive, and Embedded Processing Solutions
• Rich, balanced portfolio (ASICs, Application-Specific Standard Products and Multi-Segment Products)
• A pioneer and visionary leader in sustainability

CLICK HERE TO APPLY

SiConTech hiring experienced VLSI engineers - multiple posts

Various Jobs available at present are :

SOC/IP DFT lead

• Should have had experience of DFT architecture development and coming up with DFT plan for a complex SOC from scratch

• Should be driven to achieve coverage/other DFT goals and still drive team to meet schedule constraints

• Good understanding of other domains and how they are affected or affect DFT

• Should have good post silicon DFT bringup and debug experience. Should have decent tester exposure

• Good communication and managerial skills, should be able to drive the team

• Ready for challenges and open to constraints and advices

SOC/IP Verification lead

• Lead a team of 10 people for verification closure at SoC and block level.

• Guide team to create verification plans at module and chip level for complex SOC`s.

• Should have excellant communication and managerial skills

• Should have basic knowledge of other domains like Design, DFT and Physical design

• Should have deep knowledge and experience on starting from scratch and building verification environment design and environment.

• Should have good understanding of specman.

SOC/IP Physical Design lead

• Proven experience of complex SOC in a position of accountability and not just task runner

• Thorough understanding and knowledge of the entire Back end flow

• Should have work experience in the latest technology nodes, 45nm atleast if not 32/28nm

• Should be familiar with low-power design and their impact on Back end flow

• Good communication and managerial skills, should be able to drive the team

• Ready for challenges and should be open to constraints and advices

ASIC Physical Design Engineer

• Should be an expert in complete Backend flow from Synthesis, Constraints to Physical Verification.

• Should have hands on experience in IO and power planning, Timing Optimization, CTS, Reliability closure.

• Power Management knowledge will be a plus.

• Requires expertise in tools from Synthesis to Physical Verification on any of the industry standard vendors Synopsys, Magma or Cadence

• Understanding of Formal verification, Power Integrity, Reliability like Signal EM, Xtalk, Antenna etc., is required.

SOC/IP DFT Engineer

• Good Basic understanding of all concepts of DFT including scan, ATPG, Memory Testing, I/O testing, Analog testing etc.

• Should have hands on experience of SCAN, ATPG (stuck-at and TFT mininum)

• Well versed with test protocols like JTAG and/or IEEE1500

• Should have used industry standard DFT tools from either Mentor, Synopsys or Cadence.

• Good DFT verification skills covering RTL and GLS simulation debug would be a plus point.

• Theoretical/practical knowledge of advanced fault models and low power DFT concepts would be a plus point

Analog Design and Layout Engineers

• Hands on strong experience with CMOS analog circuit design and modeling in 65nm or lower.

• Knowledge in the analog design of high speed PHYs like USB/HDMI/CAMERA/DISPLAY etc.

• Need to have design/layout experience in some but not all OPAMPs, compensators, biasing circuits, equalizers, PLLs, CDRs, high speed drivers, FIR drivers, MUX and Demux, ADC, DAC.

• should have experience with at least one of the latest Analog design tools.

• Should have knowledge of spice.

Analog Layout Engineers

• 1-5 years experience in analog/mixed-signal layout.

• Familiar with Cadence.Laker back-end design tools (Virtuoso, VirtuosoXL, Assura DRC/LVS).

• Knowledge of analog layout from top level floorplanning down to complex block level layouts.

• A basic understanding of analog IC design and processing.

• The ability to exchange and communicate information with management, analog design engineers, and peers.

SOC/IP RTL Engineer

• RTL IP assembly knowledge. Understanding of IPXACT a plus.

• Hands on experience of coding in Verilog and VHDL.

• Understanding of Power Intent, Power estimation and checks.

• Experience of Design rule checks and Clock domain crossing checks using Spyglass or similar tool.

• Specification writing.

• IP RTL development experience.

• Good knowledge of version control tools like Clearcase and Design sync.

SOC/IP Design Verification Engineer

• Develop test bench at module and chip levels using verification platforms and tools based on specman/system Verilog.

• Develop efficient system/chip level test and regression environments using scripting languages.

• Generate the test cases and run simulations to achieve code and functional coverage goals.

• Engage with design team to communicate and fix the bugs field during the verification.

• Understanding of code coverage analysis, system modeling and functional modeling a plus

ASIC STA Engineer

• Should have good timing concepts and able to close timing of Block/SoC independently.

• Should have hands on experience in constraint generation

• Hands on experience in Logical synthesis

• Knowledge in Formal Verification

• Should able to generate and implement functional Ecos

• Should have experience in Pre-layout and Post layout timing analysis

• Hands on experience in crosstalk timing closure.

• Knowledge in Path based analysis, AOCV, DMSA is a plus.

• Knowlege in complete physical Design flow is a plus.

To apply please send your resume to careers@sicontech.com (Resumes in PDF or DOC format) 

OR

CLICK HERE TO APPLY