Mentor Graphics hiring freshers as Associate Applications Engineer – DFT at Bangalore

Mentor Graphics is a global technology leader in Electronic Design Automation, providing software and hardware design solutions that help engineers around the world innovate. Each year, our customers use tools of Mentor Graphics to push the boundaries of technology to deliver smaller, faster and more reliable products. They trust us with their technologies, we trust you to make them better. 

Job Description :

Company : Mentor Graphics

Job Title : Associate Applications Engineer – DFT – 2066

Job Location : India - Bangalore

Job Category : College

Job Details :

• In this position, you will be involved in a structured Associate Rotation Engineer Training Program. This is a fast-track training program that challenges you to develop the expertise needed to solve difficult technical problems.
• Associate Rotational Engineers are members of a team of highly motivated individuals working with customers designing the most complex hardware and software systems in the world and whose applications span the electronics industry. This training program will give you unique insight into our product marketing divisions and sales organization. Upon successful completion of the training program, you will be eligible to advance into one of these organizations.

Job Qualifications :

Requirements : 

Education : 

• BSEE/MSEE (Masters degree is preferred) Familiar with VLSI design, HDL Synthesis, VLSI testing and design for testability. 

Experience :

• Experience with design, simulation, verification of ASIC/VLSI circuits and systems, design verification and product test generation preferred.
• In-depth understanding of Design for Test (DFT) structures is required. 
• This includes scan based testing, Memory BIST, Logic BIST, and Boundary Scan (1149.1). Knowledge of scan data compression methodologies desired. 

Preferred experience in specific areas : 

• Operating Systems : UNIX, Linux, Sun Solaris. 
• Languages : Verilog (Behavioral, RTL, gate level), VHDL (Behavioral, RTL, gate level), Perl, C/C++. 
• CAD Tools : Synthesis, Simulation, ATPG, Memory BIST, Logic BIST, Boundary Scan. Familiarity with FastScan, FlexTest, LBISTArchitect, MBISTArchitect, and BSDArchitect a plus. 
• Strong trouble shooting skills and ability to break a complex problem into its components. 
• Excellent verbal and written communication skills
• very self-motivated and results-oriented
• Travel maybe required

CLICK HERE TO APPLY

Synopsys hiring B. Tech ECE / EEE freshers at Hyderabad and Bangalore

Business Title : CAE

Requisition Number : 5787BR

Hiring Locations :

INDIA - Bangalore

INDIA - Hyderabad

Job Category : Engineering

Hire Type : Employee

Job Description and Requirements :

Provides post-sales technical expertise during the installation, implementation, and maintenance of company products. May be involved in implementing detailed customer installation requirements. Ensures that client’s needs have been met and that the product/solution is fully functioning according to specification. May provide pre-sales support to company sales staff and customer personnel. The primiary responsibility will be to develop DRC/LVS/Fill/ERC runsets for IC Validator.

Has a basic overall understanding of the design process. Strong communication skills are required. Is proficient with UNIX, basic circuit layouts nd has a strong understanding of ASIC design flow, VLSI, and/or CAD engineering. Knowledge of competitive EDA tool products and product knowledge in any of the areas of Synthesis, Simulation, Verification, Place and Route, Design Reuse and/or Physical Design is preferred.

Typically requires no previous professional experience. Knowledge base generally acquired from a college degree or equivalent course training. Learns to use professional concepts. Applies company policies and procedures to resolve routine issues. Follows standard practices and specific, outlined, and detailed procedures in analyzing situations or data from which answers can be readily obtained. Normally receives detailed instructions on work, which is reviewed regularly by manager or more senior peers. Builds routine working relationships internally. Contacts are primarily with direct manager and other peers in the group or department.

About the company :

http://www.synopsys.com

Synopsys Inc. (Nasdaq:SNPS) provides products and services that accelerate innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor intellectual property (IP), Synopsys' comprehensive, integrated portfolio of system-level, IP, implementation, verification, manufacturing, optical and field-programmable gate array (FPGA) solutions help address the key challenges designers face such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in quickly bringing the best products to market while reducing costs and schedule risk. For more than 25 years, Synopsys has been at the heart of accelerating electronics innovation with engineers around the world having used Synopsys technology to successfully design and create billions of chips and systems. The company is headquartered in Mountain View, California, and has approximately 90 offices located throughout North America, Europe, Japan, Asia and India.

CLICK HERE TO APPLY

Intel Internship for Mtech students at Bangalore

Job Title : Intern - VP IP Design and Verification

Location : Bangalore

Experience : 0-1 Yrs

Qualification : 

• Mtech student with good academic background from reputed institution (IIT/REC/RVCE/reputed university/college). 
• Should be available on site for one year project duration minimum 3 days a week for first six months. 
• Followed by this next six months possibly 5 days a week. E & C / CS is preferable. 
• Should have good analytical and programming skill set. 
• Programming in C and C++ is must. Hands on SystemC programming language is a plus.

Job Description :

Virtual Platform IP design and verification, release. Shall understand specification of the Intel Mobile chipset identified IP, develop the IP using programming language SystemC , develop test bench environment , test cases. Shall independently verify the developed IP, provide technical presentation to the lead on IP design, verification coverage, test results. Should have good analytical and programming skill set.Strong digital design skillset must. Programming in C and C++ is must. Hands on SystemC programming language is a plus.

About the company :

http://www.intel.in

Intel Technology India Pvt.Ltd focuses on creating innovative products that advance the next generation of technology. Intel with its strong technology heritage, provides an opportunity to work on cutting-edge technology, pushing the boundaries of innovation and transforming the way people live and work.

XILINX hiring Junior ESL-Simulation Research Engineer

Job Title : Junior ESL-Simulation Research Engineer

Location : India

Detailed Description :

Xilinx Inc., the world’s leading provider of All Programmable FPGAs, SoCs and 3D ICs, is looking for a self-motivated, dedicated and stable individual with keen interest for niche technology in the field of System Level Simulation Tools for Xilinx FPGAs. Xilinx’s Vivado Software Suite facilitates Electronic System Level integration and simulation for Xilinx FPGAs. Vivado software suite supports design simulation using in-house and third-party simulation tools.

The candidate will assist senior members of the team in contribution to architecture, design, execution and quality of the product through major initiatives driven in ESL simulation team. The candidate will prototype and productize innovative concepts to speed up System Level Simulation by several orders of magnitude. He will also be execution hand to senior members of the team in developing integration modules with cross-geographic teams such as Vivado IP Integrator, Vivado HLS, Vivado System Generator, IP and Simulation teams besides playing key role in idea sales and technology change management programmes. He will be responsible for addition of new System Level Simulation features to Vivado tool-suite, integrate VHDL/Verilog and C++ simulation models and development of integration tools and simulation solutions.

The candidate will develop solid ground on various simulation techniques and will be exposed to internal idea sales process and technology change management programmes. He will collaborate with teams spread across globe and ensure speedy, accurate and coherent response to demands placed on him for execution and customer support in extremely technology focused environment encouraging innovation and execution. He will need minimal super-vision, be self-learner and good collaborator with team mates and peers.

The position is a one year contractual position extendible based on performance and business requirement

Job Requirement :

The candidate will show strong academic performance or strong performance in extra-curricular engineering activities such as engineering forums or paper publications or public engineering contests demonstrating passion for engineering sciences with minimum Bachelor degree in engineering or basic sciences with good written and oral communication skills in relevant field with 0-2 years of experience.

Skills :

Required : Academic/project work experience of Simulation technologies

1. Strong in C++ & SystemC

2. Above average in VHDL or Verilog

3. Experience of TLM and AXI bus protocols

4. Mixed language simulation

Preferred : Experience in any one or more of the following

1. Design patterns

2. Xilinx ISE or Vivado tools

3. Experience in IP Design environment in standards based environment involving IP X-ACT, TCL based architecture

In addition knowledge of languages such TCL, shell-scripting, cygwin, Visual Studio, perforce, SVN is advantageous.

CLICK HERE TO APPLY

LSI Bangalore internship in PDK validation for new college graduates

Requisition Number : 13-10741

Job Title : Intern for PDK validation

Country : India

State/Province/County : Karnataka

City : Bangalore

Job Description : 

Qualifications : 

• New College Gradudate with BE in ECE or Masters in Microelectronics /VLSI design with good academic record.
• Should be interested in working on validating design components used in Physical design kits, work on Scripting for Automation and running device level simulations.

About the company :

www.lsi.com

LSI designs semiconductors and software that accelerate storage and networking in datacenters, mobile networks and client computing. Our technology is the intelligence critical to enhanced application performance, and is applied in solutions created in collaboration with our partners.

CLICK HERE TO APPLY

CDAC recruiting BE / BTech/ ME / MTech / PhD as Project Engineers

Job Title :  Project Engineer - I & Project Engineer - II.

Job Location : Hyderabad

Qualification : BE / BTech/ ME / MTech / PhD 

Salary : Rs. 31000 & Rs. 37000 (FIXED)

Last Date : 15-01-2013 (05:00 P.M)

 About CDAC Hyderabad:

C-DAC, Hyderabad is a Knowledge centre with the components of Knowledge Creation, Knowledge Dissemination, Knowledge Application to grow in the areas of Research & Development, Training and Business respectively. The R & D areas of the centre are e-Security, Embedded Systems, Ubiquitous Computing, e-Learning and ICT for Development

The centre has developed over a period of time a number of products and solutions, such as EnSafe, RealSafe, e-Sikshak, e-Savya, CET Automation Tool, Quality Assurance Analytics Tool for e-Learning etc. The centre has established a number of labs in cutting edge technologies like e-Suraksha Concept Lab, Malware Resource Centre, Ubiquitous Research Centre, Walk-in e-Learning Technology Laboratory, etc.

The centre has also actively involved in ICT for development through its Multilingual "India Development Gateway (InDG)" Web Portal. The centre has also taken initiative for creating Mass Awareness in Information Security

In line with these R&D strengths, the centre also offers Post Graduate level diploma courses in the areas of Network Security, Embedded Systems, VLSI, System Software Development, Advanced Business Computing etc.

 

CLICK HERE FOR DETAILS

Only online submission of application is allowed. Candidates are required to apply online, take print out of auto generated filled application format, paste their photograph at the appropriate place, put their signature at the designated place and send it to The HRD Officer, CDAC, No.1, Shivbag, Ameerpet, Hyderabad-500 016 along with Demand Draft. 

Fees:

A Demand Draft for Rs. 100/- (for each post)  issued from any Nationalised Banks drawn in  favour of C-DAC  Hyderabad and payable at Hyderabad is to be enclosed. Candidates are advised to write their name, application no., address & contact no. on the reverse side of the DD. No application fee needs to be paid by the candidates belonging to SC/ST/Physically Challenged category.  If any fee (DD) enclosed/submitted by the above category, will not be refunded.

CLICK HERE FOR DETAILS

SiConTech hiring experienced VLSI engineers - multiple posts

Various Jobs available at present are :

SOC/IP DFT lead

• Should have had experience of DFT architecture development and coming up with DFT plan for a complex SOC from scratch

• Should be driven to achieve coverage/other DFT goals and still drive team to meet schedule constraints

• Good understanding of other domains and how they are affected or affect DFT

• Should have good post silicon DFT bringup and debug experience. Should have decent tester exposure

• Good communication and managerial skills, should be able to drive the team

• Ready for challenges and open to constraints and advices

SOC/IP Verification lead

• Lead a team of 10 people for verification closure at SoC and block level.

• Guide team to create verification plans at module and chip level for complex SOC`s.

• Should have excellant communication and managerial skills

• Should have basic knowledge of other domains like Design, DFT and Physical design

• Should have deep knowledge and experience on starting from scratch and building verification environment design and environment.

• Should have good understanding of specman.

SOC/IP Physical Design lead

• Proven experience of complex SOC in a position of accountability and not just task runner

• Thorough understanding and knowledge of the entire Back end flow

• Should have work experience in the latest technology nodes, 45nm atleast if not 32/28nm

• Should be familiar with low-power design and their impact on Back end flow

• Good communication and managerial skills, should be able to drive the team

• Ready for challenges and should be open to constraints and advices

ASIC Physical Design Engineer

• Should be an expert in complete Backend flow from Synthesis, Constraints to Physical Verification.

• Should have hands on experience in IO and power planning, Timing Optimization, CTS, Reliability closure.

• Power Management knowledge will be a plus.

• Requires expertise in tools from Synthesis to Physical Verification on any of the industry standard vendors Synopsys, Magma or Cadence

• Understanding of Formal verification, Power Integrity, Reliability like Signal EM, Xtalk, Antenna etc., is required.

SOC/IP DFT Engineer

• Good Basic understanding of all concepts of DFT including scan, ATPG, Memory Testing, I/O testing, Analog testing etc.

• Should have hands on experience of SCAN, ATPG (stuck-at and TFT mininum)

• Well versed with test protocols like JTAG and/or IEEE1500

• Should have used industry standard DFT tools from either Mentor, Synopsys or Cadence.

• Good DFT verification skills covering RTL and GLS simulation debug would be a plus point.

• Theoretical/practical knowledge of advanced fault models and low power DFT concepts would be a plus point

Analog Design and Layout Engineers

• Hands on strong experience with CMOS analog circuit design and modeling in 65nm or lower.

• Knowledge in the analog design of high speed PHYs like USB/HDMI/CAMERA/DISPLAY etc.

• Need to have design/layout experience in some but not all OPAMPs, compensators, biasing circuits, equalizers, PLLs, CDRs, high speed drivers, FIR drivers, MUX and Demux, ADC, DAC.

• should have experience with at least one of the latest Analog design tools.

• Should have knowledge of spice.

Analog Layout Engineers

• 1-5 years experience in analog/mixed-signal layout.

• Familiar with Cadence.Laker back-end design tools (Virtuoso, VirtuosoXL, Assura DRC/LVS).

• Knowledge of analog layout from top level floorplanning down to complex block level layouts.

• A basic understanding of analog IC design and processing.

• The ability to exchange and communicate information with management, analog design engineers, and peers.

SOC/IP RTL Engineer

• RTL IP assembly knowledge. Understanding of IPXACT a plus.

• Hands on experience of coding in Verilog and VHDL.

• Understanding of Power Intent, Power estimation and checks.

• Experience of Design rule checks and Clock domain crossing checks using Spyglass or similar tool.

• Specification writing.

• IP RTL development experience.

• Good knowledge of version control tools like Clearcase and Design sync.

SOC/IP Design Verification Engineer

• Develop test bench at module and chip levels using verification platforms and tools based on specman/system Verilog.

• Develop efficient system/chip level test and regression environments using scripting languages.

• Generate the test cases and run simulations to achieve code and functional coverage goals.

• Engage with design team to communicate and fix the bugs field during the verification.

• Understanding of code coverage analysis, system modeling and functional modeling a plus

ASIC STA Engineer

• Should have good timing concepts and able to close timing of Block/SoC independently.

• Should have hands on experience in constraint generation

• Hands on experience in Logical synthesis

• Knowledge in Formal Verification

• Should able to generate and implement functional Ecos

• Should have experience in Pre-layout and Post layout timing analysis

• Hands on experience in crosstalk timing closure.

• Knowledge in Path based analysis, AOCV, DMSA is a plus.

• Knowlege in complete physical Design flow is a plus.

To apply please send your resume to careers@sicontech.com (Resumes in PDF or DOC format) 

OR

CLICK HERE TO APPLY

TRYLOGIC looking for fresher / experienced professionals - multiple jobs

Current Job Opportunities:

TRY LOGIC looking for fresher / experienced professionals on following domain: 

• Corporate Trainer (Adv.JAVA,J2EE,J2ME / .NET 4.0 / JOOMLA / BIZTALK / SHAREPOINT / INFORMATICA / UNIX /DWH / DATAMINING / CLOUD COMPUTING / VLSI / MATLAB) Full time (or) Part time

• Project Guide(s) for Academic Institutional Purpose (Full Time only)

• Trainer / Mentor (In-house and Client site): Adv.JAVA,J2EE / .NET 3.5 & 4.0 / PHP / JOOMLA /BIZTALK / SHAREPOINT / INFORMATICA / UNIX / DWH / DATAMINING / CLOUD COMPUTING / VLSI / EMBEDDED SYSTEMS/MATLAB/AUTO-CAD (CIVIL & MECHANICAL) (Full time (or) Part time)

• Software Developers Experienced only (01-03 years) .NET / J2SE 

• Technical Consultant (Fresher (or) Experienced) - SAP (All Modules) 

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• Trainee Developers in .NET 3.5/4.0, JAVA, ANDROID

• Support Engineer(s) - Mainframes 

• Trainee Developers in Advanced Java (Good Knowledge in SWINGS is must)

• Associate Engineers (.NET Framework ( 3.5/4.0), ANDROID TECHNOLOGIES, JAVA TECHNOLOGIES, EMBEDDED SYSTEMS 

• Developer - PL/SQL Programming (or) Oracle & Web Services)

• MANAGER, ASST.MANAGER, TRAINEE EXCUTIVE'S to work on CORPORATE RELATIONS (full-time MBA, Male candidates only) 

• FRONT-OFFICE ADMIN MANAGER (Female Candidates only- MUST HAVE PRIOR EXPERIENCE)

For all the above mentioned positions, adequate knowledge on Technology, good aptitude and positive attitude, communication skills, analytical ability, problem solving and analyzing skills is mandatory.

Educational Qualification:

BE /B.Tech /BCA /M.Tech /MCA /M.Sc /MIT /3 years NIIT (or) APTECH Degree or formal degree in Computer science or Information technology or Electronics is suitable for IT and Engineering divisions, ECE, EEE & CIVIL Engineering graduates please apply for EMBEDDED, AUTOCAD based positions.

If your credentials match with our requirements, send your CV to ravi@trylogic.in

Internship at Synopsys in VLSI domain.

JOB tITLE : INTERN
LOCATION : BANGALOTRE
Description:

The focus of work would be in one of the following areas:USB2/USB3/Ethernet

The nature of work would be on the following lines:
Architecture exploration of the sub-blocks within one of these IPs to optimize for area, speed and power
VLSI Design & verification of these sub-blocks/exploration of latest features and standards

Requirements:

HDL Languages coding experience preferably in Verilog/Vera/System Verilog is preferable.
The candidate must have completed Bachelors degree in electronics/ Electrical engg. Partial completion of MS/MTech preferable.

FOR MORE DETAILS CLICK HERE