Job Title :
Junior ESL-Simulation Research Engineer
Location : India
Detailed Description :
Xilinx Inc., the world’s leading provider of All Programmable FPGAs, SoCs and 3D ICs, is looking for a self-motivated, dedicated and stable individual with keen interest for niche technology in the field of System Level Simulation Tools for Xilinx FPGAs. Xilinx’s Vivado Software Suite facilitates Electronic System Level integration and simulation for Xilinx FPGAs. Vivado software suite supports design simulation using in-house and third-party simulation tools.
The candidate will assist senior members of the team in contribution to architecture, design, execution and quality of the product through major initiatives driven in ESL simulation team. The candidate will prototype and productize innovative concepts to speed up System Level Simulation by several orders of magnitude. He will also be execution hand to senior members of the team in developing integration modules with cross-geographic teams such as Vivado IP Integrator, Vivado HLS, Vivado System Generator, IP and Simulation teams besides playing key role in idea sales and technology change management programmes. He will be responsible for addition of new System Level Simulation features to Vivado tool-suite, integrate VHDL/Verilog and C++ simulation models and development of integration tools and simulation solutions.
The candidate will develop solid ground on various simulation techniques and will be exposed to internal idea sales process and technology change management programmes. He will collaborate with teams spread across globe and ensure speedy, accurate and coherent response to demands placed on him for execution and customer support in extremely technology focused environment encouraging innovation and execution. He will need minimal super-vision, be self-learner and good collaborator with team mates and peers.
The position is a one year contractual position extendible based on performance and business requirement
Job Requirement :
The candidate will show strong academic performance or strong performance in extra-curricular engineering activities such as engineering forums or paper publications or public engineering contests demonstrating passion for engineering sciences with minimum Bachelor degree in engineering or basic sciences with good written and oral communication skills in relevant field with 0-2 years of experience.
Skills :
Required : Academic/project work experience of Simulation technologies
1. Strong in C++ & SystemC
2. Above average in VHDL or Verilog
3. Experience of TLM and AXI bus protocols
4. Mixed language simulation
Preferred : Experience in any one or more of the following
1. Design patterns
2. Xilinx ISE or Vivado tools
3. Experience in IP Design environment in standards based environment involving IP X-ACT, TCL based architecture
In addition knowledge of languages such TCL, shell-scripting, cygwin, Visual Studio, perforce, SVN is advantageous.
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