SiConTech hiring experienced VLSI engineers - multiple posts

Various Jobs available at present are :

SOC/IP DFT lead

• Should have had experience of DFT architecture development and coming up with DFT plan for a complex SOC from scratch

• Should be driven to achieve coverage/other DFT goals and still drive team to meet schedule constraints

• Good understanding of other domains and how they are affected or affect DFT

• Should have good post silicon DFT bringup and debug experience. Should have decent tester exposure

• Good communication and managerial skills, should be able to drive the team

• Ready for challenges and open to constraints and advices

SOC/IP Verification lead

• Lead a team of 10 people for verification closure at SoC and block level.

• Guide team to create verification plans at module and chip level for complex SOC`s.

• Should have excellant communication and managerial skills

• Should have basic knowledge of other domains like Design, DFT and Physical design

• Should have deep knowledge and experience on starting from scratch and building verification environment design and environment.

• Should have good understanding of specman.

SOC/IP Physical Design lead

• Proven experience of complex SOC in a position of accountability and not just task runner

• Thorough understanding and knowledge of the entire Back end flow

• Should have work experience in the latest technology nodes, 45nm atleast if not 32/28nm

• Should be familiar with low-power design and their impact on Back end flow

• Good communication and managerial skills, should be able to drive the team

• Ready for challenges and should be open to constraints and advices

ASIC Physical Design Engineer

• Should be an expert in complete Backend flow from Synthesis, Constraints to Physical Verification.

• Should have hands on experience in IO and power planning, Timing Optimization, CTS, Reliability closure.

• Power Management knowledge will be a plus.

• Requires expertise in tools from Synthesis to Physical Verification on any of the industry standard vendors Synopsys, Magma or Cadence

• Understanding of Formal verification, Power Integrity, Reliability like Signal EM, Xtalk, Antenna etc., is required.

SOC/IP DFT Engineer

• Good Basic understanding of all concepts of DFT including scan, ATPG, Memory Testing, I/O testing, Analog testing etc.

• Should have hands on experience of SCAN, ATPG (stuck-at and TFT mininum)

• Well versed with test protocols like JTAG and/or IEEE1500

• Should have used industry standard DFT tools from either Mentor, Synopsys or Cadence.

• Good DFT verification skills covering RTL and GLS simulation debug would be a plus point.

• Theoretical/practical knowledge of advanced fault models and low power DFT concepts would be a plus point

Analog Design and Layout Engineers

• Hands on strong experience with CMOS analog circuit design and modeling in 65nm or lower.

• Knowledge in the analog design of high speed PHYs like USB/HDMI/CAMERA/DISPLAY etc.

• Need to have design/layout experience in some but not all OPAMPs, compensators, biasing circuits, equalizers, PLLs, CDRs, high speed drivers, FIR drivers, MUX and Demux, ADC, DAC.

• should have experience with at least one of the latest Analog design tools.

• Should have knowledge of spice.

Analog Layout Engineers

• 1-5 years experience in analog/mixed-signal layout.

• Familiar with Cadence.Laker back-end design tools (Virtuoso, VirtuosoXL, Assura DRC/LVS).

• Knowledge of analog layout from top level floorplanning down to complex block level layouts.

• A basic understanding of analog IC design and processing.

• The ability to exchange and communicate information with management, analog design engineers, and peers.

SOC/IP RTL Engineer

• RTL IP assembly knowledge. Understanding of IPXACT a plus.

• Hands on experience of coding in Verilog and VHDL.

• Understanding of Power Intent, Power estimation and checks.

• Experience of Design rule checks and Clock domain crossing checks using Spyglass or similar tool.

• Specification writing.

• IP RTL development experience.

• Good knowledge of version control tools like Clearcase and Design sync.

SOC/IP Design Verification Engineer

• Develop test bench at module and chip levels using verification platforms and tools based on specman/system Verilog.

• Develop efficient system/chip level test and regression environments using scripting languages.

• Generate the test cases and run simulations to achieve code and functional coverage goals.

• Engage with design team to communicate and fix the bugs field during the verification.

• Understanding of code coverage analysis, system modeling and functional modeling a plus

ASIC STA Engineer

• Should have good timing concepts and able to close timing of Block/SoC independently.

• Should have hands on experience in constraint generation

• Hands on experience in Logical synthesis

• Knowledge in Formal Verification

• Should able to generate and implement functional Ecos

• Should have experience in Pre-layout and Post layout timing analysis

• Hands on experience in crosstalk timing closure.

• Knowledge in Path based analysis, AOCV, DMSA is a plus.

• Knowlege in complete physical Design flow is a plus.

To apply please send your resume to careers@sicontech.com (Resumes in PDF or DOC format) 

OR

CLICK HERE TO APPLY